The present invention relates to an input/output (I/O) control system for controlling initiation and interruption of an I/O unit.
Recently, a new concept has been introduced to an I/O channel of a computer. The new idea was outlined and described in detail in Chapter 13 and Chapter 14-17, respectively, of the "IBM System/370 Extended Architechture Principles of Operation (SA22-7085-0)" (to be referred to as literature 1 herebelow).
According to this concept, a channel transferring I/O information is dynamically determined depending on a state of the channel by a channel subsystem.
As an example of computers configured according to the principles described in literature 1 is the IBM-308.sub.x processor including an External Data Controller (EDC) as its channel subsystem. An outline of the operations of this processor has been described in the "IBM Maintenance Library: 3081/3083/3084 Processor Complex External Data Controller Introduction/Maintenance (SY-22-7087-2)" (to be referred to as literature 2 herebelow).
According to the literature 2, a start request of an I/O unit is first held in a logical control unit to which the I/O unit belongs. The EDC searches for the start request in the logical control unit and effects a detected start request. The search operation is conducted through a plurality of logical control units according to a round-robin sequence.
Referring to FIGS. 1-5, the operations will be briefly described herebelow.
FIG. 1 is a schematic block diagram illustrating an entire system in which an EDC 13 is connected via a system controller (SC) 12 to a central processor (CP) 11 and a main storage (MS) 10; moreover, the EDC 13 contains therein a channel (CH) 131 connected to an I/O control unit (CU) 142 by use of a standard interface. In FIG. 1, the CU 142 is connected via switches (SW's) 141 to two channels (CH's) 131. An I/O unit (I/O) 143 is connected to two CU's 142. As shown in this block diagram, a configuration in which an I/O unit is connected to a plurality of CU's will be referred to as a logical control unit (logical CU) herebelow, and a plurality of such logical CU's exist in a system. On the other hand, the MS10 is divided into a program area 101 and a hardware system area (HSA) 102. The program area 101 is used by ordinary programs, namely, as program and data areas; furthermore, an operation request block 103 to be described later is also provided in this area 101. The HSA area 102 is a special area to be accessed by the CP 11 and the EDC 13 and is used to provide therein a logical CU control block 104 and a subchannel block 105 to be described later. These logical CU control and subchannel blocks 104-105 are disposed in correspondence with a plurality of logical CU's and subchannels, respectively. FIGS. 2-4 are schematic diagrams illustrating configuration examples of the operation request block 103, the logical CU control block 104, and the subchannel block 105, respectively described in the literature 2.
According to the new concept of the literature 2, executions of I/O instructions are effected by use of subchannels having a one-to-one correspondence with respect to the I/O's.
A subchannel is kept in an associated subchannel block 105 as information necessary for accomplishing an I/O unit operation of an I/O related to the subchannel. This concept differs from the execution of the conventional I/O instruction as follows.
(1) The control program initiating operation of an I/O unit does not consider the status of the channels. A start instruction is effected with a specified subchannel, and a channel path to the I/O unit is actually selected by the hardware (EDC in this example).
(2) If the path to the I/O is busy, the hardware attempts to search for another path and to initiate operation of the I/O unit. If the hardware cannot detect an available path, the hardware keeps the start request and waits for an available path.
In FIG. 1, the I/O initiate processing is accomplished as follows. The CP 11 fetches a control program from the MS 10 for execution. If the fetched instruction is an I/O initiate instruction (Start Subchannel (SSCH) instruction), the contents of the operation request block 103 of FIG. 2 are transferred to the subchannel block 105 corresponding to the subchannel specified by the SSCH instruction. The operation request block 103 contains information such as a channel program (CCW) address. FIG. 4 is a schematic diagram illustrating a configuration example of a subchannel block in which S and I are bits indicating a start and an interruption, respectively. The contents of the transferred operation request block 103 are stored in a portion of a store area storing the subchannel control information. Another area of the subchannel control information store area is beforehand loaded with fixed information including an ISC, a logical CU number, etc. for an I/O unit. The logical CU number indicates an address of a logical CU to which an I/O unit associated with the pertinent subchannel belongs. When the operation request block 103 is transferred, an I/O start request is enqueued to the related logical CU based on the logical CU number.
A method for enqueuing the I/O start request to the CU is as follows. A top of subchannel number and a bottom of subchannel number of the subchannels waiting for a start request are stored in the logical CU control block 104, a next chained subchannel number is stored in the subchannel block 105, and the S bit indicating that a start request is being held is set to "1", thereby forming a queue chain.
FIG. 5 is a schematic diagram depicting a case in which two start requests are enqueued to a logical CU block and the queue count indicates "2" accordingly.
Among the subchannels waiting for a start request, when the top of subchannel is subchannel a and the next subchannel is subchannel b, the top of subchannel number in the logical CU block 104 indicates the subchannel a; moreover, the next subchannel number in the block of subchannel a indicates the block of subchannel b. Since a logical CU includes a plurality of I/O's, a queue may be formed in a logical CU block as shown in this example. Furthermore, a plurality of logical CU's are contained in the overall system and a queue of I/O start requests is created in each logical CU block.
The EDC 13 has a function to dequeue the queue thus created and to actually start the I/O 143. The EDC 13 accesses the MS 10 to read and update the subchannel block 105 and the logical CU control block 104. Since these blocks are accessed by the CP 11 and EDC 13, there is provided in a portion of the MS 10 the HSA area 102 for storing these blocks. The HSA area 102 is separated from the area 101 used by ordinary programs. As shown in FIGS. 3-4, the blocks 104-105 each have an area represented as "lock byte", which is used to prevent a contention between the accesses from the CP 11 and the EDC 13.
The EDC 13 cyclically effects a read operation for a plurality of logical CU control blocks and checks to determine whether or not the fetched logical CU control block has a subchannel registered to a queue. If this is the case (queue count.noteq.0), the EDC 13 executes a start operation by use of the top of subchannel number; otherwise, the EDC 13 reads the next logical CU control block and repeats the same processing.
When the EDC 13 fetches a queue, an I/O unit is initiated according to the subchannel control information in the subchannel block 105 and the channel address (CH.sub.0, CH.sub.1, CH.sub.8, and CH.sub.9 of FIG. 3) in the logical CU control block 104. If the paths of all channels are busy, the request is enqueued agained.
Although the I/O start requests in the queue are executed in a sequence depending on the SSCH instruction execution order and the logical CU number, there does not exist a clear priority for the execution. On the other hand, the control program controls the I/O operation with a priority assigned thereto; however, such a priority processing is not considered after the start instruction is once issued in the foregoing example.
Although a concept of a priority processing was adopted for an I/O interruption after a completion of an I/O processing, the conventional examples have not been flexible enough for the priority specification.